1. Field of the Invention
This invention relates to an improved data latch for sampling and storing an input data signal during a sampling time interval and for providing a corresponding output signal having one of two clearly distinguishable logic levels during a subsequent time interval.
2. Statement of the Prior Art
As known to those skilled in the art, an asynchronous input signal can be sampled and held by conventional data latching circuits. However, if during the sampling time interval, the data latching circuit receives an input signal that is undergoing a transition from, for example, a logical zero level to a logical one level, a corresponding voltage may be stored, which voltage level lies somewhere in the range between a valid logical zero and a valid logical one. As a result, during a subsequent time interval, other compatible circuits cannot distinguish between a logical zero and a logical one when receiving the stored signal from the output of a conventional data latching circuit for further signal processing. As a result, these receiving circuits would incorrectly interpret the logic level of the original sampled input signal.
Moreover, prior art data latching circuits utilize a relatively large number of components. Therefore, the required semiconductor chip area and the corresponding cost of fabrication are undesirably increased. What is more, such conventional data latching circuits consume relatively large amounts of power.
Examples of prior art clock controlled, field effect transistor flip-flop storage circuits are as follows: U.S. Pat. Nos.
3,292,008 Rapp PA1 3,624,423 Borgini PA1 3,921,011 Orgill PA1 3,983,420 Kikuchi